1. Field of the Invention
The present invention relates to a semiconductor memory device and, particularly, to a structure of wiring layers of a semiconductor memory device, which has at least two metal wiring layers.
2. Description of the Related Art
It is general that a flash memory has at least two metal wiring layers and that a wiring in each layer strides over an area between a memory cell array portion and a peripheral circuit portion to connect between them. FIGS. 5 to 7 show an example of such metal wiring layers of a conventional flash memory.
FIGS. 5 and 6 are plan views of a first metal wiring layer and a second metal wiring layer of the conventional flash memory, respectively. In these figures, a square area 601 is a memory cell array portion and a peripheral circuit portion is arranged in an area 602 surrounding the memory cell array portion 601. As shown in FIG. 5, the first metal wiring layer includes bit lines 603 and wirings 604 for the peripheral circuit portion 602. The bit lines 603 stride over a border area between the memory cell array portion 601 and the peripheral circuit portion 602. The second metal wiring layer includes wirings 703, which back word lines, and wirings 704 for the peripheral circuit portion 602, as shown in FIG. 6. The wirings 703 stride over the border area between the memory cell array portion 601 and the peripheral circuit portion 602 in a direction perpendicular to the direction of the bit lines 603 in the first metal wiring layer.
FIG. 7 is cross sections taken along a line D-D' in FIGS. 5 and 6 in an overlapped relation, showing a region in the vicinity of the border area between the memory cell array portion and the peripheral circuit portion. A flash memory having double layer gates is formed in the memory cell array portion 601. Reference numerals 801 and 802 depict a control gate and a floating gate of the flash memory, respectively. The control gate 801 has a polycide structure. A plurality of peripheral transistors each having a single layer gate are formed in the peripheral circuit portion 602. A reference numeral 803 depicts a gate electrode of each of the peripheral transistors. An interlayer insulating film 804 is formed on the gate electrode of each peripheral transistor and flattened by CMP (chemical-mechanical polishing), with a step 806 being left in the boarder portion between the memory cell array portion 601 and the peripheral circuit portion 602. The step 806 is caused by a difference in height between the flash memory cell having the double layer gates 801 and 802 and the peripheral transistor having the single layer gate 803 and such large step is usually left even when the interlayer insulating film is flattened by CMP. Since the bit lines 603 are formed on the interlayer insulating film 804 and stride over the border area between the memory cell array portion 601 and the peripheral circuit portion 602, the bit lines are also formed on the step 806. An interlayer insulating film 805 is further formed on the bit lines 603 and flattened by CMP similarly to the interlayer insulating film 804, with a step 807 being left in the boarder portion between the memory cell array portion 601 and the peripheral circuit portion 602. The wirings 703, which back word lines, and the wirings 704 for the peripheral circuit portion 602 are formed on the interlayer insulating film 805. The wirings 703 stride over the area between the memory cell array portion 601 and the peripheral circuit portion 602 in a cross section taken perpendicularly to that shown in FIG. 7 and is also formed on the step 807.
As described, in the flash memory, there are the steps 806 and 807 formed in the interlayer insulating films on the border portion due to the difference in height between the gates of the transistors of the memory cell array portion 601 and the gates of the transistors of the peripheral circuit portion 602 and, when CMP is performed to flatten the interlayer insulating films, the step 806 of, particularly, the first interlayer insulating film 804 becomes as large as 80 nm. Since, in the conventional technology, the wirings (bit lines 603) are formed on the border portion in which the large step 806 exists, there is a problem.
That is, the bit lines 603 are formed by forming a metal film of such as aluminum on a whole surface of the interlayer insulating film 804 and patterning the metal film by etching. In etching the metal film, a portion of the metal film tends to be left non-etched on the area in which there is the large step 806. When there is such metal film portion left non-etched on the area, there may be a possibility of short-circuit between adjacent wirings. Therefore, according to the conventional technology, a margin has to be provided in a distance between adjacent wirings, causing the distance to be about 0.5 .mu.m or more. Consequently, it becomes difficult to reduce a cell area of the semiconductor memory device.